Integration of low and high voltage devices on substrate

ABSTRACT

The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

REFERENCE TO RELATED APPLICATIONS

This Application is a Divisional of U.S. application Ser. No.17/574,728, filed on Jan. 13, 2022, which claims the benefit of U.S.Provisional Application No. 63/220,167, filed on Jul. 9, 2021. Thecontents of the above-referenced Patent Applications are herebyincorporated by reference in their entirety.

BACKGROUND

Modern day integrated chips comprise millions or billions ofsemiconductor devices formed on a semiconductor substrate (e.g.,silicon). Integrated chips (ICs) may use many different types ofsemiconductor devices, depending on an application of an IC. To reducethe area of the IC, the semiconductor devices with differing thresholdvoltages may be formed in close proximity to one another.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a cross-sectional view of some embodiments of forminga semiconductor structure including a first well region and a secondwell region formed according to a single well mask.

FIG. 2 illustrates a top view of some embodiments of forming thesemiconductor structure as indicated by cut-lines A-A′ in FIGS. 1 and 2.

FIG. 3 illustrates a cross-sectional view of some embodiments of asemiconductor structure including a first well region with a pluralityof first regions separated by a plurality of second regions.

FIG. 4 illustrates a top view 400 of some embodiments of thesemiconductor structure 300 as indicated by cut-lines A-A′ in FIGS. 3and 4 .

FIG. 5 illustrates a top view of some alternative embodiments of asemiconductor structure including a plurality of first regions separatedby a plurality of second regions that are parallel to a longest lengthof a gate electrode.

FIG. 6 illustrates a top view of some alternative embodiments of asemiconductor structure including a plurality of first regions separatedby a plurality of second regions that are rotated relative to a longestlength of a gate electrode.

FIG. 7 illustrates a cross-sectional view of some embodiments of asemiconductor structure including a well region of a semiconductordevice with a plurality of first regions separated by a plurality ofsecond regions.

FIG. 8 illustrates a top view of some embodiments of the semiconductorstructure as indicated by cut-lines A-A′ in FIGS. 7 and 8 .

FIGS. 9-16 illustrate cross-sectional and top views of some embodimentsof methods of forming a semiconductor device with a first well regioncomprising a plurality of first regions separated by a plurality ofsecond regions where the first well region is formed according to asingle well mask.

FIG. 17 illustrates a flow diagram of some embodiments of a method forforming a first device with a first well region comprising a pluralityof first regions separated by a plurality of second regions is provided.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Integrated circuit includes semiconductor devices with differingthreshold voltages integrated in one substrate and in close proximity toone another. For example, various semiconductor devices may have high,medium, and low threshold voltages, or fine-tuned threshold voltage in acertain range. Forming devices that operate at different thresholdvoltages on one substrate is costly when multiple well masks andmultiple implantation processes are needed. For example, forming abipolar complementary metal oxide semiconductor double diffused metaloxide semiconductor (BCD) device comprises many complex manufacturingsteps including multiple masking and implantation steps. Such complexmanufacturing steps used to form BCD type devices or multiple devices ofdifferent threshold or control voltages reduce fabrication efficiency,result in high process costs, and may also introduce damage to thedevices on the same substrate.

Various embodiments of the present disclosure relate to a semiconductordevice with a gate overlying a well region comprising a plurality offirst regions separated by a plurality of second regions in asemiconductor substrate. The plurality of first regions can include afirst dopant, and the plurality of second regions can include a seconddopant that is different from the first dopant. The first dopant andsecond dopant can, for example, be different dopant types or differentdopant concentrations. By forming the well region with the plurality offirst regions and the plurality of second regions, a threshold voltageof the semiconductor device can be controlled according to a dopingdensity, a doping type, and a geometry of the plurality of first andsecond regions. Laterally offset from the gate is a source/drain with asource/drain dopant different than the first dopants and the seconddopant. In some aspects, the source/drain overlie the plurality of firstregions and the plurality of second regions.

In some embodiments, semiconductor devices operating at differentthreshold voltages, are formed in the semiconductor substrate. The wellregions of the semiconductor devices can be formed according to a singlemask with a plurality of slits separated by a plurality of widths, thatafter undergoing a doping process, result in the plurality of firstregions separated by the plurality of second regions respectively forthe semiconductor devices. Thus, the well regions of the semiconductordevices are formed according to the single mask where the one or moresemiconductor devices can be formed respectively with a unique thresholdvoltage that can be different from one another. As such, the differentthreshold voltages associated with the semiconductor devices arerealized by forming different geometries of the first regions and thesecond regions of the well regions without the use of multiple maskingsteps.

FIG. 1 illustrates a cross-sectional view of some embodiments of forminga semiconductor structure 100 including a first well region 116 (alsoreferred to as a well region) and a second well region 110 formedaccording to a single well mask 134.

The semiconductor structure 100 comprises a single well mask 134disposed over a semiconductor substrate 102. The single well mask 134may be or comprise, for example, photoresist, silicon nitride, or someother suitable mask material. In some embodiments, a process for formingthe single well mask 134 comprises depositing a mask layer andsubsequently patterning the mask layer into the single well mask 134. Inembodiments in which the mask layer is a photoresist, the patterningmay, for example, be performed using photolithography or some othersuitable process. The semiconductor substrate 102 may be or comprise,for example, silicon (Si), a monocrystalline silicon, germanium (Ge),silicon-germanium (SiGe), gallium arsenide (GaAs), some othersemiconductor material, or a combination thereof.

The single well mask 134 comprises a plurality of slits 132 that extendthrough the single well mask. The plurality of slits 132 exposes topsurfaces of a first well region 116 of a first device 128 and topsurfaces of a second well region 110 of a second device 130. The firstdevice 128 and the second device 130 can respectively be a semiconductordevice (e.g. metal oxide semiconductor field effect transistor (MOSFET)or a laterally-diffused metal-oxide semiconductor (LDMOS) device). Insome aspects, the first device 128 and the second device 130 aredifferent semiconductor devices. For example, the first device 128 canbe the MOSFET, while the second device 130 can be the LDMOS device. Theplurality of slits 132 over the first well region 116 are of a firstslit width 124 and separated by a first mask width 122 (sometimesreferred to as a mask width). The plurality of slits 132 over the secondwell region 110 are of a second slit width 114 and separated by a secondmask width 112.

A doping process 104 is performed through the plurality of slits 132 ofthe single well mask 134 to form the first well region 116 and thesecond well region 110 in the semiconductor substrate 102. The dopingprocess 104 can include a second dopant that is different than a dopingof the semiconductor substrate 102. In some embodiments, the seconddoping and the doping of the semiconductor substrate 102 can be of thesame doping type (e.g., n-type or p-type) and different dopingconcentration or density. In other embodiments, the second doping andthe doping of the semiconductor substrate 102 are of a different dopingtype. The doping process 104 forms a plurality of first regions 118separated by a plurality of second regions 120 of the first device 128and a plurality of first regions 106 separated by a plurality of secondregions 108 of the second device 130. The plurality of first regions118, 106 and the plurality of second regions 120, 108, extend from a topsurface of the semiconductor substrate 102 to a bottom surface of thefirst well region 116 and the second well region 110.

In embodiments where the first device 128 and the second device 130 havedifferent threshold voltages, the first slit width 124 and second slitwidth 114 are different, and/or the first mask width 122 and the secondmask width 112 are different. As such, different doping profiles areachieved for the first device 128 and the second device 130 bycontrolling the first slit width 124, the second slit width 114, thefirst mask width 122, and the second mask width 112, and the thresholdvoltage of the first device 128 and the second device 130 are controlledseparately according to the single well mask 134 and doping process 104.

FIG. 2 illustrates a top view 200 of some embodiments of forming thesemiconductor structure 100 as indicated by cut-lines A-A′ in FIGS. 1and 2 . The top view 200 shows cut-lines A-A′ through the single wellmask 134. The plurality of slits 132 are arranged in a horizontaldirection covering the first well region 116 and the second well region110.

FIG. 3 illustrates a cross-sectional view of some embodiments of asemiconductor structure 300 including a first well region 116 with aplurality of first regions 118 separated by a plurality of secondregions 120.

The semiconductor structure 300 comprises an interlayer dielectric (ILD)layer 304 disposed over a semiconductor substrate 102. A first device128 (e.g. metal oxide semiconductor field effect transistor (MOSFET)) isdisposed in the ILD layer 304 and the semiconductor substrate 102. Insome embodiments, the first device 128 is the same as the first device128 of FIG. 1 . The ILD layer 304 may comprise a low-k dielectric (e.g.,a dielectric material with a dielectric constant less than about 3.9),an oxide (e.g., SiO₂), a nitride (e.g., SiN), an oxy-nitride (e.g.,SiON), undoped silicate glass (USG), doped silicon dioxide (e.g., carbondoped silicon dioxide), borosilicate glass (BSG), phosphoric silicateglass (PSG), borophosphosilicate glass (BPSG), fluorinated silicateglass (FSG), a spin-on glass (SOG), or the like.

A first well region 116 is disposed within the semiconductor substrate102 where the well region comprises a plurality of first regions 118separated by a plurality of second regions 120. In some embodiments, theplurality of first regions 118 separated by the plurality of secondregions 120 is formed according to the single well mask 134 of FIG. 1 .The first well region 116 extends from a top surface of thesemiconductor substrate 102 into the semiconductor substrate 102. Theplurality of first regions 118 and the plurality of second regions 120extend vertically from a top surface of the first well region 116 to abottom surface of the first well region 116. The plurality of firstregions 118 have a first width 322 and the plurality of second regions120 have a second width 324 that is different than the first width 322.In some embodiments, the first width 322 and the second width 324 can bethe same. It is understood that while the plurality of first and secondregions 118, 120 are depicted to comprise a number of elements perregion, the number of elements per region can be more or less.

The plurality of first regions 118 comprise a first doping and theplurality of second regions 120 comprise a second doping that isdifferent from the first doping. In some embodiments, the second dopingof the plurality of second regions 120 is formed according to the dopingprocess 104 of FIG. 1 . In some embodiments, the first doping and thesecond doping can be of the same doping type (e.g., n-type or p-type)and different doping concentration or density. In other embodiments, thefirst doping and the second doping are of a different doping type. Inyet other embodiments, the first doping can be the same as a doping ofthe semiconductor substrate 102 or different than the doping of thesemiconductor substrate 102.

A gate dielectric 310 is disposed over the first well region 116 in theILD layer 304 between the first well region 116 and a gate electrode312. In some embodiments, the gate dielectric 310 and the gate electrode312 are collectively referred to as a gate stack. The gate stackoverlies a portion of the plurality of first and second regions 118,120. In some embodiments, the gate electrode 312 is or comprisespolysilicon. In some embodiments, the gate electrode 312 may be orcomprise a metal, such as aluminum (Al), copper (Cu), titanium (Ti),tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), or the like.In such embodiments, the gate dielectric 310 may be or comprise a high-kdielectric material, such as hafnium oxide (HfO), tantalum oxide (TaO),hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HMO), aluminumoxide (AlO), zirconium oxide (ZrO), or the like.

A source 306 and a drain 308 are laterally offset from the gateelectrode 312 on opposing sides of the gate electrode 312. The source306 and the drain 308 extends laterally over a subset of the pluralityof first and second regions 118, 120 from a first top surface of theplurality of first and second regions 118, 120 to above a second topsurface of the plurality of first and second regions 118, 120. One ormore of the plurality of first and second regions 118, 120 have a curvedsurface along one or more of the source 306 and the drain 308. Thesource 306 and the drain 308 can, for example, comprise the same dopingtype. The first device 128 comprises the gate stack, the source 306, thedrain 308, and the first well region 116.

A shallow trench isolation (STI) structure 326 extends from a topsurface of the semiconductor substrate 102 to below the bottom surfaceof the first well region 116. In alternative embodiments, the STIstructure 326 extends to above the bottom surface of the first wellregion 116. The STI structure 326 abuts an outer edge of the first wellregion 116. The STI structure 326 can provide isolation between thefirst device 128 and other devices, for example, the second device 130of FIG. 1 . The STI structure 326 may, for example, be or comprise adielectric material (e.g., silicon dioxide), a low-k dielectric, or thelike. The ILD layer 304 comprises conductive contacts 314 that extendthrough the ILD layer 304 to contact the source 306, the drain 308, andthe gate electrode 312. The conductive contacts 314 may, for example, beor comprise, tungsten (W), copper (Cu), aluminum (Al), or the like. Theconductive contacts 314 are configured to provide electrical connectionsbetween various devices of an integrated chip (IC).

FIG. 4 illustrates a top view 400 of some embodiments of thesemiconductor structure 300 as indicated by cut-lines A-A′ in FIGS. 3and 4 .

The top view 400 shows that the plurality of first and second regions118, 120 extends in a lateral direction perpendicular to a longestlength of the gate electrode 312. Furthermore, the plurality of firstand second regions 118, 120 extends laterally past outer edges of thegate electrode 312, the source 306, and the drain 308.

The first width 322 of the plurality of first regions 118, the secondwidth 324 of the plurality of second regions 120, the first doping ofthe plurality of first regions 118, and the second doping of theplurality of second regions 120 can collectively be referred to asvoltage control parameters and relate to a threshold voltage of thefirst device 128. The voltage control parameters can be chosen torealize a desired threshold voltage of the first device 128 where thedesired threshold voltage may be different than other devices. Thevoltage control parameters of the first device 128 and other devices(e.g. the second device 130 of FIG. 1 ) can be realized according to asingle well mask (e.g. the single well mask 134 of FIG. 1 ) wheredifferent threshold voltages on a per device basis is achieved.

FIG. 5 illustrates a top view 500 of some alternative embodiments of asemiconductor structure 300 including a plurality of first regions 118separated by a plurality of second regions 120 that are parallel to alongest length of a gate electrode 312.

The top view 500 shows that the plurality of first and second regions118, 120 extends in a lateral direction parallel to a longest length ofthe gate electrode 312. Furthermore, the plurality of first and secondregions 118, 120 extend laterally past outer edges of the gate electrode312, the source 306, and the drain 308. In some aspects, a longest edgeof the source 306 or the drain 308 overlaps with one of the plurality ofsecond regions 120 and a longest edge of the gate electrode 312 overlapswith one of the plurality of first regions 118. The longest edge of thesource 306 or the drain 308 and the longest edge of the gate electrode312 are not limited in this respect and could overlap with the pluralityof first regions 118 and the plurality of second regions 120 indifferent ways.

FIG. 6 illustrates a top view 600 of some alternative embodiments of asemiconductor structure 300 including a plurality of first regions 118separated by a plurality of second regions 120 that are rotated relativeto a longest length of a gate electrode 312.

The top view 600 shows that the plurality of first and second regions118, 120 extend in a lateral direction at an angle relative to a longestlength of the gate electrode 312. Top view 600 shows the angle as 45degrees, however, the angle is not limited in this respect and canrepresent a rotation relative to a longest length of the gate electrode312 greater than 0 degrees and less than 180 degrees.

FIG. 7 illustrates a cross-sectional view of some embodiments of asemiconductor structure 700 including a well region 716 of asemiconductor device 730 with a plurality of first regions 718 separatedby a plurality of second regions 720.

The semiconductor structure 700 comprises an ILD layer 704 disposed overa semiconductor substrate 702. The ILD layer 704 can correspond to theILD layer 304 of FIG. 3 and the semiconductor substrate 702 cancorrespond to the semiconductor substrate 102 of FIG. 1 . Asemiconductor device 730 is disposed in the ILD layer 704 and thesemiconductor substrate 702. In some embodiments, the semiconductordevice 730 is a LDMOS device and can correspond, for example, to thesecond device 130 of FIG. 1 .

A well region 716 is disposed within the semiconductor substrate 702where the well region 716 comprises a plurality of first regions 718separated by a plurality of second regions 720. In some embodiments, thewell region 716, the plurality of first regions 718, and the pluralityof second regions 720 correspond to the second well region 110, theplurality of first regions 106, and the plurality of second regions 108respectively of FIG. 1 . The well region 716 extends from a top surfaceof the semiconductor substrate 702 to above a bottom surface of thesemiconductor substrate 702 and the plurality of first and secondregions 718, 720 extend vertically from a top surface of the well region716 to a bottom surface of the well region 716. The plurality of firstregions 718 have a first width 722 and the plurality of second regions720 have a second width 724 that is different than the first width 722.In some embodiments the first width 722 and the second width 724 can bethe same.

The plurality of first regions 718 comprise a first doping and theplurality of second regions 720 comprise a second doping that isdifferent from the first doping. In some embodiments, the second dopingof the plurality of second regions 720 is formed according to the dopingprocess 104 of FIG. 1 . In some embodiments, the first doping and thesecond doping can be of the same doping type (e.g., n-type or p-type)and different doping concentration or density. In other embodiments, thefirst doping and the second doping are of a different doping type. Inyet other embodiments, the first doping can be the same as a doping ofthe semiconductor substrate 702 or different than the doping of thesemiconductor substrate 702.

A gate dielectric 710 is disposed in the ILD layer 704 between the wellregion 716 and a gate electrode 712. In some embodiments, the gatedielectric 710 and the gate electrode 712 comprise the same materials asthe gate dielectric 310 and the gate electrode 312 respectively of FIG.3 . In some embodiments, the gate dielectric 710 and the gate electrode712 are collectively referred to as a gate stack. The gate stackoverlies a portion of the plurality of first and second regions 118,120.

A source 706 is laterally offset from the gate electrode 712. The source706 extends laterally over a subset of the plurality of first and secondregions 718, 720 from a first top surface of the plurality of first andsecond regions 718, 720 to above a second top surface of the pluralityof first and second regions 718, 720. One or more of the plurality offirst and second regions 718, 720 have a curved surface along a bottomsurface of the source 706. The well region 716 extends from beyond anoutermost edge of the source 706 to under the gate electrode 712 betweenoutermost edges of the gate electrode 712.

A STI structure 732 is disposed within the semiconductor substrate 702extending from the top surface of the semiconductor substrate 702 toabove the bottom surface of the well region 716. The STI structure 732extends from under the gate electrode 712 past an outermost edge of thegate electrode 712. The STI structure 732 may, for example, be orcomprise a dielectric material (e.g., silicon dioxide), a low-kdielectric, or the like.

A drain 708 is disposed in the semiconductor substrate 702 and extendsfrom the top surface of the semiconductor substrate. The drain 708 isseparated from the well region 716 and the gate electrode 712 by the STIstructure 732. The drain 708 and the STI structure 732 are disposedwithin a drift region 734 that extends from an outer edge of the wellregion 716 to the drain 708 within the semiconductor substrate 702. Insome embodiments a doping of the drift region 734 can be the same as adoping of the semiconductor substrate 702, in other embodiments thedoping of the drift region 734 is different than the doping of thesemiconductor substrate 702. The semiconductor device 730 comprises thegate stack, the source 706, the drain 708, the well region 716, and theSTI structure 732.

A STI structure 726 extends from a top surface of the semiconductorsubstrate 702 to below a bottom surface of the well region 716. The STIstructure 726 abuts an outer edge of the well region 716 and the drain708. The STI structure 726 may, for example, be or comprise a dielectricmaterial (e.g., silicon dioxide), a low-k dielectric, or the like. TheILD layer 704 comprises conductive contacts 714 that extend through theILD layer 704 to contact the source 706, the drain 708, and the gateelectrode 712. The conductive contacts 714 may, for example, be orcomprise, tungsten (W), copper (Cu), aluminum (Al), or the like.

FIG. 8 illustrates a top view 800 of some embodiments of thesemiconductor structure 700 as indicated by cut-lines A-A′ in FIGS. 7and 8 .

The top view 800 shows the plurality of first and second regions 718,720 extending in a lateral direction perpendicular to a longest lengthof the gate electrode 312. The plurality of first and second regions718, 720 extend laterally past outer edges of the gate electrode 712,and past outer edges of the source 706. Outermost edges of the pluralityof first and second regions 718, 720 extend from outside the outer edgeof the gate electrode 712 to a region within the outer edge of the gateelectrode. In alternative embodiments, the plurality of first and secondregions 718, 720 can extend in lateral directions parallel or angularlyrotated relative to the longest length of the gate electrode 312, asdepicted in FIGS. 5 and 6 .

In some embodiments, the semiconductor device 730 can be the seconddevice 130 of FIG. 1 where the well region 716 (analogous to second wellregion 110 of FIG. 1 ) can be formed from the single well mask 134 ofFIG. 1 simultaneously with the first well region 116 of FIG. 1 . Athreshold voltage of the semiconductor device 730 can be different thanthe threshold voltage of the first device 128 where the differentthreshold voltage of both devices is realized according to the singlewell mask 134 of FIG. 1 .

FIGS. 9-16 illustrate cross-sectional and top views of some embodimentsof methods of forming a semiconductor device with a first well region116 comprising a plurality of first regions 118 separated by a pluralityof second regions 120 where the first well region 116 is formedaccording to a single well mask 134. Although the cross-sectional views900-1600 shown in FIGS. 9-16 are described with reference to a method,it will be appreciated that the structures shown in FIGS. 9-16 are notlimited to the method but rather may stand alone separate of the method.Furthermore, although FIGS. 9-16 are described as a series of acts, itwill be appreciated that these acts are not limited in that the order ofthe acts can be altered in other embodiments, and the methods disclosedare also applicable to other structures. In other embodiments, some actsthat are illustrated and/or described may be omitted in whole or inpart. Also, alternative embodiments depicted in FIGS. 1-9 may besubstituted for embodiments in FIGS. 9-16 although they may not beshown.

As shown in cross-sectional view 900 of FIG. 9 , a single well mask 134is formed over a semiconductor substrate 102. The semiconductorsubstrate 102 may be or comprise, for example, Si, a monocrystallinesilicon, Ge, SiGe, GaAs, some other semiconductor material, or acombination thereof.

In some embodiments, the single well mask 134 may, for example, bedeposited by a physical vapor deposition (PVD), a chemical vapordeposition (CVD), or an atomic layer deposition (ALD) process, and maybe or comprise a silicon-based material, such as silicon nitride.Forming the single well mask 134 includes a patterning process (notshown). The patterning process may, for example, comprise any of aphotolithography process and an etching process. In some embodiments(not shown), a photoresist is formed over the single well mask 134. Thephotoresist is patterned by an acceptable photolithography technique todevelop an exposed photo resist. With the exposed photo resist in place,an etch is performed to transfer the pattern from the exposed photoresist to the underlying layers, for example, the single well mask 134,to form a plurality of slits 132 that extend through the single wellmask 134. The etching process may comprise a wet etching process, a dryetching process, or some other suitable etching process. The pluralityof slits 132 expose top surfaces of the semiconductor substrate 102. Theplurality of slits 132 are of a first slit width 124 separated by afirst mask width 122.

FIG. 10 illustrates a top view 1000 of some embodiments of thecross-sectional view 900 of FIG. 9 as indicated by cut lines A-A′through the single well mask 134 in FIGS. 9 and 10 .

As seen in the top view 1000, the plurality of slits 132 are arranged ina horizontal direction creating a plurality of rectangles defined by thefirst slit width 124 separated by the first mask width 122. In someembodiments the plurality of slits 132 are arranged in a paralleldirection analogous to the plurality of first and second regions of FIG.5 , in further embodiments the plurality of slits 132 are rotatedanalogous to the plurality of first and second regions of FIG. 6 .

As shown in cross-sectional view 1100 of FIG. 11 , a doping process 104is performed through the plurality of slits 132 of the single well mask134. The doping process 104 can be performed according to an ionimplantation or a diffusion process. The doping process 104 can includea second doping that is different than a doping of the semiconductorsubstrate 102. In some embodiments, the second doping and the doping ofthe semiconductor substrate 102 can be of the same doping type (e.g.,n-type or p-type) and different doping concentration or density. Inother embodiments, the second doping and the doping of the semiconductorsubstrate 102 are of a different doping type.

The doping process 104 forms a first well region 116 within thesemiconductor substrate 102 where the first well region 116 comprises aplurality of first regions 118 separated by a plurality of secondregions 120. As such, it can be said that the plurality of first regions118 and the plurality of second regions 120 form or define the firstwell region. The plurality of first regions 118 are aligned below thefirst mask width 122 of the single well mask 134 that separate theplurality of slits 132. The plurality of first regions 118 have a firstwidth 322 that is the same as the first mask width 122. The plurality ofsecond regions 120 are aligned below the plurality of slits 132. Theplurality of second regions 120 have a second width 324 that is the sameas the first slit width 124. The plurality of second regions 120 are ofthe second doping according to the doping process 104.

In some embodiments, the plurality of first regions 118 are of a firstdoping and the same as a doping of the semiconductor substrate 102. Insome embodiments, the first doping and the second doping can be of thesame doping type (e.g., n-type or p-type) and different dopingconcentration or density. In other embodiments, the first doping and thesecond doping are of a different doping type. In yet other embodiments,the first doping can be different than the doping of the semiconductorsubstrate 102.

By forming the plurality of first and second regions 118, 120 with thesingle well mask 134 in place with the plurality of slits 132, dopingprofiles of various devices can be separately formed by, e.g.controlling the first mask width 122 and the plurality of slits 132 forof the various devices. By controlling the first mask width 122 and theplurality of slits 132 for the various devices, different thresholdvoltages can be realized according to the single well mask 134 anddoping process 104.

As shown in cross-sectional view 1200 of FIG. 12 , the single well mask(134 of FIG. 11 ) is removed. The single well mask (134 of FIG. 11 )may, for example, be removed through a chemical wash process, an etchprocess, a planarization process, an ashing process, or other suitableremoval process. After removing the single well mask (134 of FIG. 11 ),STI structure 326 is formed in the semiconductor substrate 102 abuttingan outer edge of the first well region 116. The STI structure 326 may beformed by selectively etching the semiconductor substrate 102 (notshown) to form a trench in the semiconductor substrate 102, andsubsequently filling the trench with a dielectric material. Thedielectric material may, for example, be or comprise a dielectricmaterial (e.g., silicon dioxide), a low-k dielectric, or the like. Infurther embodiments, the semiconductor substrate 102 is selectivelyetched by forming a masking layer (not shown) over the semiconductorsubstrate 102, and subsequently exposing the semiconductor substrate 102to an etchant configured to selectively remove unmasked portions of thesemiconductor substrate 102.

A gate dielectric layer 1202 is deposited over the semiconductorsubstrate 102, the STI structure 326, and the first well region 116. Thegate dielectric layer 1202 may, for example, be or comprise, a high-kdielectric material, such HfO, TaO, HfSiO, HfTaO, AlO, ZrO, or the like.A gate electrode layer 1204 is formed over the gate dielectric layer1202. The gate electrode layer 1204 may, for example, be or comprise ametal, such as Al, Cu, Ti, Ta, W, Mo, Co, or the like. A gate mask 1206is deposited over the gate electrode layer 1204. The gate mask 1206 may,for example, be or comprise a silicon-based material, such as siliconnitride. The gate dielectric layer 1202, the gate electrode layer 1204,and the gate mask 1206 may, for example, be deposited by a PVD, CVD, orALD process.

As shown in cross-sectional view 1300 of FIG. 13 , the gate dielectriclayer (1202 of FIG. 12 ), the gate electrode layer (1204 of FIG. 12 ),and the gate mask 1206 are patterned to form a gate electrode 312 and agate dielectric 310. The gate electrode 312 and the gate dielectric 310can be referred to as a gate stack.

In some embodiments, a process for forming the gate stack comprisesforming a patterned masking layer (not shown) on the gate mask 1206. Invarious embodiments, the patterned masking layer may be formed by a spinon process and patterned using photolithography. In further embodiments,the process comprises performing an etch into the gate dielectric layer(1202 of FIG. 12 ), the gate electrode layer (1204 of FIG. 12 ), and thegate mask 1206 with the patterned masking layer in place, andsubsequently stripping the patterned masking layer. In yet furtherembodiments, the gate dielectric layer (1202 of FIG. 12 ), the gateelectrode layer (1204 of FIG. 12 ), and the gate mask 1206 are patternedby a single patterning process. In other embodiments, a plurality ofpatterning process is performed to pattern the gate dielectric layer(1202 of FIG. 12 ), the gate electrode layer (1204 of FIG. 12 ), and thegate mask 1206. The gate stack is formed over a portion of the pluralityof first and second regions 118, 120.

As shown in cross-sectional view 1400 of FIG. 14 , the gate mask 1206 isremoved and a source/gate mask 1402 is deposited over the gate stack,the first well region 116, the STI structure 326, and the semiconductorsubstrate 102. In some embodiments, the source/gate mask 1402 may, forexample, be deposited by a PVD, a CVD, or an ALD process, and may be orcomprise a silicon-based material, such as silicon nitride. In someembodiments, the source/gate mask is patterned to expose source/gatedoping openings 1406. The patterning process (not shown) may, forexample, comprise any of a photolithography process and an etchingprocess. In some embodiments (not shown), a photoresist is formed overthe source/gate mask 1402. The photoresist is patterned by an acceptablephotolithography technique to develop an exposed photo resist. With theexposed photo resist in place, an etch is performed to transfer thepattern from the exposed photo resist to the underlying layers, forexample, the source/gate mask 1402, forming source/gate doping openings1406 that extend through the source/gate mask 1402. The etching processmay comprise a wet etching process, a dry etching process, or some othersuitable etching process.

The source/gate doping openings 1406 expose an upper surface of theplurality of first and second regions 118, 120 on opposing sides of thegate stack. The source/gate doping openings 1406 extend from opposingsides of the gate stack to an outer region of the plurality of first andsecond regions 118, 120. The source/gate doping opening 1406 undergo asource/drain doping process 1404. The source/drain doping process 1404can be performed according to an ion implantation or a diffusionprocess. The source/drain doping process 1404 can include a dopantdifferent than the first dopant of the plurality of first regions andthe second dopant of the plurality of second regions.

As shown in cross-sectional view 1500 of FIG. 15 , the source/draindoping process (1404 of FIG. 14 ) forms a source 306 and a drain 308under the source/gate mask (1402 of FIG. 14 ). The source 306 and thedrain 308 are formed on opposing sides of the gate stack. The source 306and the drain 308 are formed extending from top surface of the firstwell region 116 extending into the first well region 116 above a bottomsurface of the first well region 116. The source 306 and the drain 308are also formed with a curved surface contacting the first well region116. As such, the source/drain doping process (1404 of FIG. 14 ) resultsin a second upper surface of the plurality of first and second regions118, 120 that is below a first upper surface of the plurality of firstand second regions 118, 120 that is level with the top surface of thesemiconductor substrate 102. Furthermore, the second upper surface ofthe plurality of first and second regions 118, 120 is curved beneath thesource 306 and the drain 308. The first well region 116, the source 306,the drain 308, and the gate stack form a first device 128.

An ILD layer 304 is deposited over the semiconductor substrate 102, theSTI structure 326, the source 306, the drain 308, and the gate electrode312 and gate dielectric 310. The ILD layer 304 may, for example, bedeposited by a PVD, CVD, or ALD process, and may comprise a low-kdielectric, an oxide, a nitride, an oxy-nitride, undoped silicate glass,doped silicon dioxide, borosilicate glass, phosphoric silicate glass,borophosphosilicate glass, fluorinated silicate glass, a spin-on glass,or the like.

Conductive contacts 314 are formed in the ILD layer 304 and extendthrough the ILD layer 304 and contact the source 306, the gate electrode312, and the drain 308. In some embodiments, a process for forming theconductive contacts 314 (not shown) comprises forming a masking layercovering the ILD layer 304. The masking layer is patterned with a layoutof the conductive contacts 314, and an etch is performed into the ILDlayer 304 with the patterned masking layer in place to form contactopenings corresponding to the conductive contacts 314. The patterningmay be, for example, performed by photolithography or some otherpatterning process. A conductive layer is then deposited covering theILD layer 304 and filling the contact openings, and a planarizationprocess is performed into the conductive layer until the ILD layer 304is reached. The conductive layer may be deposited by, for example, CVD,PVD, ALD, sputtering, electroless plating, electroplating, or some otherdeposition or plating process. The planarization process may be, forexample, a chemical-mechanical planarization (CMP) process or some othersuitable planarization process. In various embodiments, the process maybe part of a single damascene like process or a dual damascene likeprocess. The conductive contacts 314 may, for example, be or comprise,W, Cu, Al, or the like. Conductive contacts 314 (right and left) areformed over the source 306 and drain 308 respectively and over thesecond upper surface of the plurality of first and second regions 118,120.

FIG. 16 illustrates a top view 1600 of some embodiments of thecross-sectional view 1500 of FIG. 15 as indicated by cut lines A-A′. Thegate electrode 312, source 306, and drain 308 are shown as transparentfor illustrative purposes. The plurality of first and second regions118, 120 are formed in a lateral direction perpendicular to a longestlength of the gate electrode 312 and extend laterally past outer edgesof the gate electrode 312, the source 306, and the drain 308. Inalternative embodiments, the plurality of first and second regions 118,120 can extend in lateral directions parallel or angularly rotatedrelative to the longest length of the gate electrode 312, as depicted inFIGS. 5 and 6 and would correspond to the plurality of slits (132 ofFIG. 10 ) being formed horizontally or rotated as discussed previouslyin FIG. 10 .

FIGS. 9 through 16 show the formation of the first device 128 with thefirst well region 116 formed from a single well mask 134 comprising aplurality of slits 132 separated by the first mask width 122. The dopingprocess 104 results in formation of the plurality of first regions 118separated from the plurality of second regions 120 which control thethreshold voltage of the first device 128. Furthermore, the thresholdvoltage of the first device and a threshold voltages of other devices(e.g. the second device 130 of FIG. 1 ) can be controlled according tothe single well mask 134 where the threshold voltage of the first deviceand the threshold voltages of other devices are different without theneed of multiple well masking steps.

FIG. 17 illustrates a flow diagram of some embodiments of a method 1700for forming a first device with a first well region 116 comprising aplurality of first regions 118 separated by a plurality of secondregions 120 is provided.

At act 1702, a single well mask is deposited over a semiconductorsubstrate and patterned to form a plurality of slits separated by aplurality of first mask width. FIGS. 9 and 10 illustrate cross-sectionalview 900 and top view 1000 respectively corresponding to someembodiments of act 1702.

At act 1704, a doping process is performed through the plurality ofslits to form a plurality of first regions separated by a plurality ofsecond regions within a first well region. FIGS. 9 and 11 illustratecross-sectional views 900 and 1100 corresponding to some embodiments ofact 1704.

At act 1706, the single well mask is removed and a STI structure isformed in the semiconductor substrate abutting an outer edge of thefirst well region and a gate dielectric and gate electrode are formedover the first well region. The gate dielectric and gate electrode forma gate stack. FIGS. 12 and 13 illustrate cross-sectional views 1200 and1300 corresponding to some embodiments of act 1706.

At act 1708, a source/gate mask is deposited and patterned over the gatestack, the first well region, the STI structure, and semiconductorsubstrate to form source/gate doping openings over the first wellregion, laterally offset from the gate stack. FIG. 14 illustratescross-sectional view 1400 corresponding to some embodiments of act 1708.

At act 1710, a source/drain doping process is performed through thesource/gate doping openings to form a source and a drain within thefirst well region. FIG. 14 illustrates cross-sectional view 1400corresponding to some embodiments of act 1710.

At act 1712, the source/gate mask is removed and an ILD layer isdeposited over the semiconductor substrate, first well region, STIstructure, source, and drain. Conductive contacts are formed through theILD layer that couple to the gate electrode, source, and drain. FIGS. 15and 16 illustrate cross-sectional views 1500 through 1600 respectivelycorresponding to some embodiments of act 1712.

Although the method 1700 is illustrated and/or described as a series ofacts or events, it will be appreciated that the method 1700 is notlimited to the illustrated ordering or acts. Thus, in some embodiments,the acts may be carried out in different orders than illustrated, and/ormay be carried out concurrently. Further, in some embodiments, theillustrated acts or events may be subdivided into multiple acts orevents, which may be carried out at separate times or concurrently withother acts or sub-acts. In some embodiments, some illustrated acts orevents may be omitted, and other un-illustrated acts or events may beincluded.

In various embodiments, the present application provides a semiconductorstructure including: a well region disposed within a semiconductorsubstrate; the well region including a plurality of first regionsseparated by a plurality of second regions, where the plurality of firstregions are of a first doping and the plurality of second regions are ofa second doping different than the first doping; and a gate electrodeoverlying the well region where the gate electrode is disposed laterallyover a portion of the plurality of first regions and a portion of theplurality of second regions.

In various embodiments, the present application provides a semiconductorstructure including: a well region disposed within a semiconductorsubstrate; the well region including a plurality of first regionsseparated by a plurality of second regions; and a gate electrodeoverlying the well region where the plurality of first regions andplurality of second regions extend vertically beneath the gate electrodefrom a top surface of the well region to a bottom surface of the wellregion.

In various embodiments, the present application provides a method offorming a semiconductor structure, including: forming a single well maskover a semiconductor substrate; patterning the single well mask to forma plurality of slits separated by a mask width; performing a dopingprocess on the semiconductor substrate through the single well mask toform a well region where a dopant of the doping process is differentthan a dopant of the semiconductor substrate; where the doping processforms a plurality of first regions aligned under the mask width andseparated by a plurality of second regions aligned under the pluralityof slits where the plurality of first regions and the plurality ofsecond regions form the well region; and forming a drain and a sourcewithin the well region; and forming a gate electrode over the wellregion.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor structure comprising: a wellregion disposed within a semiconductor substrate; the well regioncomprising a plurality of first regions separated by a plurality ofsecond regions, wherein the plurality of first regions are of a firstdoping and the plurality of second regions are of a second dopingdifferent than the first doping; and a gate electrode overlying the wellregion wherein the gate electrode is disposed laterally over a portionof the plurality of first regions and a portion of the plurality ofsecond regions.
 2. The semiconductor structure of claim 1, furthercomprising a source wherein the source is disposed laterally over asubset of the plurality of first regions and a subset of the pluralityof second regions.
 3. The semiconductor structure of claim 2, wherein atop surface of the source is level with a first top surface of theplurality of first regions and wherein a bottom surface of the source isabove a second top surface of the plurality of first regions.
 4. Thesemiconductor structure of claim 2, wherein a top surface of theplurality of first regions or a top surface of the plurality of secondregions are curved.
 5. The semiconductor structure of claim 1, wherein awidth of the plurality of first regions is different than a width of theplurality of second regions.
 6. The semiconductor structure of claim 1,wherein the plurality of first regions extends in a lateral directionperpendicular to a longest length of the gate electrode.
 7. Thesemiconductor structure of claim 6, further comprising a gate dielectricbetween the gate electrode and the well region, wherein the gatedielectric is disposed within an interlayer dielectric (ILD) layer thatoverlies the semiconductor substrate.
 8. The semiconductor structure ofclaim 7, further comprising a shallow trench isolation (STI) structuredisposed within the semiconductor substrate, wherein the STI structurelaterally surrounds the plurality of first regions and the plurality ofsecond regions.
 9. A semiconductor structure comprising: a well regiondisposed within a semiconductor substrate; the well region comprising aplurality of first regions separated by a plurality of second regions;and a gate electrode overlying the well region wherein the plurality offirst regions and plurality of second regions extend vertically beneaththe gate electrode from a top surface of the well region to a bottomsurface of the well region.
 10. The semiconductor structure of claim 9,wherein the plurality of first regions are of a first dopingconcentration and the plurality of second regions are of a second dopingconcentration different than the first doping concentration.
 11. Thesemiconductor structure of claim 9, wherein the plurality of secondregions extends laterally past an outer edge of the gate electrode. 12.The semiconductor structure of claim 9, further comprising a source or adrain laterally offset from the gate electrode wherein the plurality offirst regions or the plurality of second regions extend from a bottomsurface of the source or the drain to a bottom surface of the wellregion; and the plurality of first regions or the plurality of secondregions extend laterally past an outer edge of the source or the drain.13. The semiconductor structure of claim 9, further comprising a firsttop surface of the plurality of first regions aligned beneath the gateelectrode and a second top surface of the plurality of first regionslaterally offset from the gate electrode wherein the second top surfaceof the plurality of first regions is below the first top surface of theplurality of first regions.
 14. The semiconductor structure of claim 13,further comprising a conductive contact aligned over the second topsurface.
 15. The semiconductor structure of claim 14, wherein theconductive contact is separated from the second top surface by a sourceor a drain.
 16. The semiconductor structure of claim 9, whereinoutermost edges of the plurality of first regions laterally extends fromoutside of an outer edge of the gate electrode to a region within theouter edge of the gate electrode.
 17. A semiconductor device comprising:a gate electrode overlying a semiconductor substrate; a source and adrain disposed within the semiconductor substrate extending away fromouter edges of the gate electrode; and a plurality of first regionsseparated by a plurality of second regions that extend from under thegate electrode, source, and drain, wherein a doping of the source andthe drain is different than a doping of the plurality of first regionsand the plurality of second regions, and a doping of the plurality offirst regions is different than a doping of the plurality of secondregions.
 18. The semiconductor device of claim 17, further comprising ashallow trench isolation (STI) structure disposed within thesemiconductor substrate, wherein the plurality of first regions or theplurality of second regions separates the STI structure from the sourceand the drain.
 19. The semiconductor device of claim 18, wherein at abottom surface of the STI structure, the semiconductor substrateseparates the STI structure from the plurality of first regions and theplurality of second regions.
 20. The semiconductor device of claim 17,wherein the plurality of first regions and the plurality of secondregions laterally surround the gate electrode, the source, and thedrain.